1. Field of the Invention
The present invention relates generally to microelectronic circuits, and more particularly, to electrical contacting schemes of trench gates in trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices.
2. Description of the Related Art
Power semiconductor devices have been used as power switches for various applications. Advent in semiconductor technologies enables these power devices to operate with high reliability and performance.
One type of power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device that shows prominence in application is the trench gate MOSFET power device. In a trench-gate MOSFET device, intersecting trenches which define a plurality of cells are formed in a silicon substrate. FIG. 1 is a cross-sectional view of part of a trench-gate MOSFET device signified by the reference numeral 2. There is a plurality of trenches 4 formed in a substrate 6. The trenches 4 are filled with conductive material 8 separated from the substrate 6 with a thin layer of insulating material 10. There is also a source layer 12 deposited in a body layer 17 which in turn is deposited in the semiconductor substrate 6. The source layer 12 is in contact with a source metal layer 13. An insulating layer 15 separates the conductive material 8 from the source metal layer 13. As arranged, a plurality of MOSFET cells 14 is formed in the substrate 6. Specifically, for each MOSFET cell 14, the source layer 12, the conductive material 8 and insulating material 10 constitute respectively the source, gate and gate oxide layer of a MOSFET. In addition, a lightly doped epitaxial layer 16 coupled with a heavily doped contact layer 18 attached to a drain metal layer 20 forms the common drain of the device 2.
Power MOSFET device with trench gates provide many advantages. To begin with, the channels, signified by the reference numeral 21 in FIG. 1, of the MOSFETs are arranged in a vertical manner, instead of horizontally as in most planar configurations. The consequential benefit is that a higher degree of integration on a semiconductor substrate can be realized. More importantly, since the channel direction is vertical, the lateral current paths are basically eliminated. As a result, the overall channel resistance is reduced. Reduction in channel resistance substantially curtails Ohmic loss during the power-on state of the MOSFET, which in turn provides lower power consumption and further alleviates heat dissipation.
Advantageous as it appears for a trench-gate MOSFET structure, heretofore, there have been technical complications in providing electrical contacts to the conductive material 8 inside the trenches 4.
FIG. 2 is a top plan view of an overall metallization scheme of a conventional power MOSFET structure, such as the structure 2 shown in FIG. 1. FIG. 1, as described above, is a cross-sectional view taken along the line 1—1 of FIG. 2. For clarity and conciseness in illustration, other metal layers such as the metal layers for the terminal circuits are not shown in FIGS. 1 and 2. As can be seen in FIG. 2, the source metal layer 13 is deposited on the semiconductor substrate 6 with a plurality of protruding fingers 13A. In a similar manner, the gate metal 22 is also deposited on the semiconductor substrate 6 with a plurality of protruding fingers 22A. The protruding fingers 13A and 22A electrically separate but interleave with each other on the surface of the substrate 6 as shown in FIG. 2.
FIG. 3 is an enlarged view taken within the circle 3 of FIG. 2. FIGS. 4 and 5 are cross-sectional views taken along the lines 4—4 and 5—5, respectively, of FIG. 3. FIGS. 3–5 highlight the relationship of the source metal layer 13 and the gate metal layer 22 in more details. For clarity in illustration, the metal layers and contact openings are shown in ghost lines in FIG. 3.
As shown in FIGS. 3–5, the source metal finger 13A is disposed in contact with the source layer 12. The gate metal finger 22A is disposed in contact with a poly runner 24 through a contact opening 26. The poly runner 24 is in turn deposited in contact with the conductive material 8 in the trenches 4.
There are several disadvantages associated with the metallization scheme of the conventional structure 2 as shown in FIGS. 1–5. First, the gate metal fingers 22A coupled with the poly runner 24 and the associated contacting trenches 4 use up precious semiconductor spaces on the substrate 6, which spaces could have been used for active cells 14. Furthermore, the conductive material 8 in the trenches 4, even though heavily doped, does not assume conductivity comparable to that of metal. Specifically, the material 8 in the trenches 4 with the relatively high resistivity manifests itself as distributed resistance along the gate-to-source input path, thereby undermining the timing response of the structure 2. Phrased differently, the relatively low conductivity of the material 8 retards the RC (resistance-capacitance) time constant of the gate-to-source input path of the structure 2 and renders the structure 2 not suitable for use in high-frequency applications.
It also should be emphasized that in the design of a power MOSFET, providing a lower power-on resistance RON is of paramount importance. The power-on resistance RON of a power MOSFET device is defined as the gross Ohmic resistance through the device during the power-on state. Lower power-on resistance RON not only curtails power consumption and thus cuts down wasteful heat dissipation, it also prevents the power MOSFET device from robbing away any intended driving voltage to the circuits that the MOSFET device drives. That is, lower Ohmic drop passing through the power MOSFET device during normal operation avails the target circuit driven by the MOSFET device with a less distorted driving voltage. Modern-day MOSFET power devices can now be made with power-on resistance RON in the milliohm (mΩ) range. The segmented source metal 13 unnecessarily adds source metal resistance to the overall power-on resistance RON of the structure 2.
The fabrication of the conventional structure 2 also requires a relatively tight manufacturing control. For example, the metal-to-metal separation between the source metal layer 13 and the gate metal layer 22, identified in FIGS. 3–5 as separation S, needs to be tightly controlled. Thus, if the separation S falls beyond a certain manufacturing tolerance, there is a risk of electrical shorts between the metal layers 13 and 22 and is detrimental to the production yield. To maintain the tolerance, constant monitoring is required during processing.
It also needs to be mentioned that the structure 2 does not have a relatively wide degree of flexibility during die-bonding. Reference is now directed to FIG. 2. During the die-bonding process, the electrical terminals of the structure 2, such as the source metal 13, need to be connected to a chip carrier (not shown) via the bond wires 28. As shown in FIG. 2, the bond wires 28 for the source metal layer 13 is confined to an area designated by the reference numeral 30 which is away from the gate metal fingers 22A on the substrate 6. Any mistepping of the bond wire 28 beyond the confined area 30 may result in electrical shorts between the metal fingers 13A and 22A.
Electronic products are now built with ever increasing complexity providing various functions which require high-frequency operations and critically depend on the reliable supply of power by the power devices. There has been a long-felt demand to provide dependable, responsive and robust power devices to these modern-day products without the aforementioned shortfalls.